The invention relates to a method for data transmission in which the binary original data is transmitted from a transmitter to a unit of a receiver, preferably to a register, and where the original data is transmitted through one or several data lines.
In known data transmission processes, the exchange of data is bidirectional, takes place in parallel and is based on a transmission of original data and preferably a base address also through which the unit is selected. The transmission channel (data bus) can be selected here with any width. The original data is transmitted in multiplex mode on the same lines as the base address; the base address is sent first on the data bus and then the original data. By means of the base address, the unit is selected to which the original data is to be transmitted.
In order to check whether the original data and the base address have been transmitted without error, in JP 02-113340 a parity bit is added to each data word to be transmitted, and in DE 1524 009 or JP 62-010 941 several parity bits are added, allowing certain types of transmission faults to be identified. For specific applications, however, such as the triggering of airbag systems for example, a higher degree of reliability in data transmission must be assured.
Furthermore, in JP 02-140 030 for example, a method is described for monitoring transmission from a transmitter to a receiver by sending back to the transmitter the data inverted in the receiver and by making a comparison in the transmitter after having inverted the data once again.
For applications such as the triggering of airbag systems for example, where immediate measures are initiated in the receiver, this return transmission is however unsuitable because the receiver does not immediately recognize an error when data is received. An error in transmission can possibly result in immediate and risky incorrect reactions.
Similarly to the method of double inversion, it is also possible to gate the data inverted once with the inverted data by means of a logical EXOR operation, as proposed for example for a parity test in JP 02-113340.
Another known method is that of Manchester coding where the inverted bit is transmitted in addition to the bit to be transmitted, firstly in order to detect single bit errors in data transmission and secondly for recovery of the clock pulse.
Furthermore, the method of transmitting digital data messages on two data lines in parallel is known from DE 196 01 836 A1, where the two data lines carry signal levels that are inverted with respect to each other.
The data transmission method of the kind specified at the outset is improved inasmuch as higher transmission reliability is ensured in the transmission of data, i.e. a data word is transmitted reliably from one electronic unit to another and to the greatest possible extent free of error.
This is effected by also transmitting from the transmitter to the receiver the inverted original data, referred to below as xe2x80x9cinversion dataxe2x80x9d, and, in accordance with the further development in the Subclaims, an address that is complementary to the base address, referred to below as xe2x80x9ccomplementary addressxe2x80x9d, where the transmitted inversion data and the transmitted complementary address are inverted in the receiver, and where the transmitted base address and the transmitted original data are compared bit for bit with the inverted complementary address and the inverted inversion data, and/or an exclusive OR operation between original and inversion data and also between base and complementary address has led bit serially to a logical xe2x80x9conexe2x80x9d.
Only where there is full agreement bit for bit will the transmitted original data be transmitted to the unit selected by means of the transmitted base address. In particular, no additional channels are needed for check or parity bits. Only the data transmission rate or clock frequency vary.
In the data transmission method according to the present invention, the base address and original data are transmitted twice with each transmission operation, in particular with each write operation, namely as base address with original data and as complementary address, complementary to the base address, with inversion data (inverted original data). By inverting once again the transmitted complementary address and the transmitted inversion data, and by subsequently comparing with the transmitted base address and the transmitted original data, it can be ensured that each transmitted bit is received correctly with two voltage levels (e.g. 0 V and 5 V). Line faults or disturbances are thus recognized.
When writing data to a target unit, it is necessary to perform these two transmission operations because a minimum of errors in the data results is required at the write target. For the reading operation too, it is possible to reliably input each item of information with two electrical levels.
One form of transmission can be called a self-synchronizing safety concept because with each transmission step it is specified whether the address is a base address or a complementary address. If a program were to be interrupted by an interrupt after the first transmission operation, it would be readily possible in the interrupt routine to input into the target unit. An error would be identifiable only on continuing the normal program if the data is not accepted by the target unit after the second write operation. The entire write operation would then have to be repeated.
In this preferred development, an address bit or an address line is used for this purpose to distinguish between base address and complementary address. This loss of an address line or an address bit is more than compensated in this self-synchronizing safety concept by the high transmission reliability of safely transmitting a data word from one electronic unit to the other.
A preferred embodiment of the method is characterized by the base address, the original data and the complementary address being stored temporarily until they have been compared. The individual items of data can thus be transmitted serially, e.g. via a common bus system, and compared with each other only when, for example, the inversion data is also available.
In a further development of this embodiment, the complementary address is stored according to its most significant (complementary) bit at another place than the base address. The complementary bit of the complementary address allows the base address and the complementary address to be easily distinguished and dealt with differently; in particular, they can be put into temporary storage.
In a preferred embodiment, the most significant (complementary) bit of the complementary address can be used for address coding of the unit. By means of the complementary bit it can be ensured, for example, that when the unit can be driven only via a base address then only base addresses are used for address coding of the unit.
Another preferred embodiment is characterized by outputting in the form of original data and as inverted original data (inversion data) the data that is to be output from the unit selected by means of the base address. This also allows data to be exchanged between two or more units by means of a double transmission operation.
In a further development of this embodiment, the most significant (complementary) bit of the complementary address is used for inverting data that is to be output from a unit. By means of the complementary bit of the complementary address, the base address and the complementary address and also the associated data can easily be distinguished and dealt with differently; in particular, the original data can be output inverted as inversion data.
In a further preferred embodiment of the data transmission method, the base address, the original data, the complementary address and the inversion data are transmitted on a common data bus.
The circuit arrangement has a base address temporary storage in which the transmitted base address is temporarily stored, an address temporary storage in which the transmitted complementary base address (complementary address) is temporarily stored, a data temporary storage in which the transmitted original data is temporarily stored, an inverter which inverts the transmitted complementary address and the transmitted inversion data, and a comparator which compares bit serially in each case the transmitted base address with the inverted complementary address and the transmitted original data with the inverted inversion data.
The advantages stated above for the method can be achieved with this circuit arrangement.
In an especially preferred embodiment of the circuit arrangement, the inverter and the comparator are formed together by an (n+m)-multiple XOR circuit with AND circuit on the output side. This will lead to an OK signal at the only output of the AND circuit only when every XOR circuit is, for example, positive at its output, i.e. at xe2x80x9clogical 1xe2x80x9d, to indicate that the compared data agree.
In another advantageous embodiment of the circuit arrangement, a selection device, in particular an address decoding device, is connected behind the address temporary storage to control the transmission of the original data to the unit selected via the base address. The unit corresponding to the base address can be chosen by means of this selection device, e.g. a demultiplexer.
A preferred further development of this embodiment is characterized by the selection device being preceded by an address inversion device which inverts the complementary address according to its most significant (complementary) bit.
In another embodiment of the circuit arrangement, a data inversion device is provided which outputs the data to be output from a unit selected by means of the base address in the form of original data under the base address and inversion data under the complementary address.
In an advantageous further development of this embodiment provision is made for the data inversion device being controlled by means of the complementary bit in such a way that the original data is output inverted as inversion data if the complementary bit is present.
In particular, this method and the circuit arrangement for data transmission can be applied in vehicle occupant protection systems between a central control unit and remote modules, in particular sensors and/or actuators, i.e. acceleration or precrash sensors such as distance warning radar, gas generators for airbags and belt tighteners and various distributed control units such as, for example, those for side collision recognition.
Further advantages of the invention are evident in the description and in the drawings. Equally, the features mentioned above and those given below can be applied in accordance with the invention each on its own or together with others or in any combination.
The embodiment revealed and described is not to be understood as a comprehensive listing; rather, it has an exemplary character in order to explain the invention.